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general description the max6917 provides all the features of a real-timeclock (rtc) plus a microprocessor (?) supervisory cir- cuit, nv ram controller, and backup-battery monitor function. in addition, 96 x 8 bits of static ram are avail- able for scratchpad storage. the max6917 communi- cates with a ? through an i 2 c-bus-compatible serial interface.the real-time clock/calendar provides seconds, min- utes, hours, day, date, month, and year information. the end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap years through 2099. the clock operates in either 24hr or 12hr format with an am/pm indicator. a time/date-programmable alarm function is provided with an open-drain, active-low alarm output. the ? supervisory circuit features an open-drain, active-low reset available in three different reset thresh- olds. a manual reset input and a watchdog function are included as well. the nv ram controller provides power for external sram from a backup battery plus chip-enable gating. the back- up battery also provides data retention of the on-board 96 x 8 bits of ram. an open-drain, active-low, battery-on sig- nal alerts the system when operating from a battery. the battery-test circuitry periodically tests the backup battery for a low-battery condition. an optional external resistor network selects different battery thresholds. a freshness seal prevents battery drain until the first v cc power-up.the max6917 has a crystal-fail-detect circuit and a data-valid bit. the max6917 is available in a 20-pin qsop package and is guaranteed to operate over the extended (-40? to +85?) temperature range. applications point-of-sale equipmentprogrammable logic controllers intelligent instruments fax machines digital thermostats industrial control features ? real-time clock counts seconds, minutes, hours, date, month, day of week, and year with leap-year compensation through 2099 ? fast (400khz) i 2 c-bus-compatible interface ? 96 x 8 bits of ram for scratchpad data storage ? uses standard 32.768khz, 6pf load, watchcrystal ? single-byte or multiple-byte (burst mode) datatransfer for read or write of clock registers or ram ? battery monitor and low-battery warning output internal default for lithium backup-batterytesting pins available for other backup-battery testing configurations ? dual power-supply pins for primary and backuppower ? battery-on output ? nv ram controller chip-enable gating (control of ce with reset and power valid)v out for sram power ? microprocessor supervisor with watchdog input ? programmable time/date alarm output ? data valid bit (loss of all voltage alerts user ofcorrupt data) ? crystal-fail detect ? reference output frequencies?hz and32.768khz ? small, 20-pin, qsop surface-mount package max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ________________________________________________________________ maxim integrated products 1 ordering information 19-3702; rev 1; 10/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package pkg code max6917eo30+ -40? to +85? 20 qsop e20-2 max6917eo33+ -40? to +85? 20 qsop e20-2 MAX6917EO50+ -40? to +85? 20 qsop e20-2 pin configuration and selector guide appear at end of datasheet. + denotes lead-free package. downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics(v cc = v cc(min) to v cc(max) , t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (notes 1, 2) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v batt , v cc to gnd ...............................................-0.3v to +6.0v all other pins to gnd ................................-0.3v to (v cc + 0.3v) all other pins to gnd ............................-0.3v to (v batt + 0.3v) input currentsv cc ..................................................................................200ma v batt .................................................................................20ma gnd ....................................................................................20ma all other pins ....................................................................20ma output currents v out continuous ..........................................................200ma all other outputs ............................................................20ma continuous power dissipation 20-pin qsop (derate 9.1mw/ c over t a = +70 c) .....727mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units max6917eo30 2.7 3.0 3.3 max6917eo33 3.0 3.3 3.6 operating voltage range(note 3) v cc MAX6917EO50 4.5 5.0 5.5 v max6917eo30 2.0 5.5 max6917eo33 2.0 5.5 operating voltage range batt(note 4) v batt MAX6917EO50 2.0 5.5 v v batt = 2v, v cc = 0 1 v batt = 3v, v cc = 0 1.4 v batt = 3.6v, v cc = 0 1.9 1hz, 32khzoutputs disabled; xtal fail disabled v batt = 5.5v, v cc = 0 3.8 v batt = 2v, v cc = 0 1.23 v batt = 3v, v cc = 0 1.61 v batt = 3.6v, v cc = 0 2.3 1hz, 32khzoutputs disabled; xtal fail enabled v batt = 5.5v, v cc = 0 4.08 v batt = 2v, v cc = 0 2.82 v batt = 3v, v cc = 0 4.7 v batt = 3.6v, v cc = 0 6.1 timekeeping current v batt (note 5) i batt 1hz, 32khzenabled, outputs open; xtal fail disabled v batt = 5.5v, v cc = 0 10.6 a v cc = 3.3v, v batt = 0 0.1 v cc = 3.6v, v batt = 0 0.12 1hz, 32khzenabled, outputs open; xtal fail enabled v cc = 5.5v, v batt = 0 0.2 v cc = 3.3v, v batt = 0 0.9 v cc = 3.6v, v batt = 0 0.11 active supply current v cc (note 6) i cca 1hz, 32khzoutputs disabled; xtal fail disabled v cc = 5.5v, v batt = 0 0.18 ma downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller _______________________________________________________________________________________ 3 dc electrical characteristics (continued)(v cc = v cc(min) to v cc(max) , t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (notes 1, 2) parameter symbol conditions min typ max units v cc = 3.3v, v batt = 0 27 v cc = 3.6v, v batt = 0 30 1hz, 32khzenabled, outputs open; xtal fail enabled v cc = 5.5v, v batt = 0 81 v cc = 3.3v, v batt = 0 20 v cc = 3.6v, v batt = 0 25 standby current v cc (note 5) i ccs 1hz, 32khzoutputs disabled; xtal fail disabled v cc = 5.5v, v batt = 0 76 a v out v cc = 2.7v, v batt = 0, i out = 35ma v cc - 0.2 v cc = 3.0v, v batt = 0, i out = 35ma v cc - 0.2 v out in v cc mode (note 4) v out v cc = 4.5v, v batt = 0, i out = 70ma v cc - 0.2 v v batt = 2v, v cc = 0, i out = 400a v batt - 0.02 v batt = 3v, v cc = 0, i out = 800a v batt - 0.03 v out in battery-backup mode (notes 4, 7) v out v batt = 4.5v, v cc = 0, i out = 1.5ma v batt - 0.05 v v batt -to-v cc switchover threshold v tru power-up (v cc < v rst ) switch from v batt to v cc (note 7) v batt + 0.1 v v cc -to-v batt switchover threshold v trd power-down (v cc < v rst ) switch from v cc to v batt (note 7) vbatt - 0.1 v ce_in and ce_out (figures 10, 14, 15, 16) ce_in leakage current iil, iih disabled, v cc < v rst , v ce_in = vcc or gnd -1 +1 a ce_in -to- ce_out resistance v cc = v cc(min), v ih = 0.9v cc , ce_out connected to gnd; vil = 0.1vcc, ce_out connected to vcc 46 140 ce_in -to- ce_out propagation delay t ced 50 source-impedance driver, c load = 10pf, v cc = v cc(min) , v ih = 0.9v cc , v il = 0.1v cc (note 8); measured from 50% point once_in to the 50% point of ce_out 10 20 ns reset active to ce_out high delay t rce mr high to low 2 10 50 s downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 4 _______________________________________________________________________________________ dc electrical characteristics (continued)(v cc = v cc(min) to v cc(max) , t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (notes 1, 2) parameter symbol conditions min typ max units ce_out active-low delay after v cc > v rst t rp 140 200 280 ms ce_out high voltage v oh i oh = -100a, v batt = 2v, v cc = 0, reset = low 0.8 x v batt v mr input (figure 10) v il 0.8 mr input voltage v ih 2.0 v mr pullup resistance internal pullup resistor 50 k mr minimum pulse width 1 s mr glitch immunity t gw 35 ns mr to reset delay t rd v cc = v cc(min) , v batt = 0 450 600 ns wdi input (figure 12) wdi initial timeout period v cc > v rst from rising edge of reset 1.00 1.6 2.25 s t wdl long watchdog timeout period 1.00 1.6 2.25 s watchdog timeout period t wds short watchdog timeout period 140 200 280 ms minimum wdi input pulse width t wdi 100 ns v il 0.8 wdi input threshold v ih 2.0 v wdi input-leakage current v wdi = v cc or gnd -100 +100 na v cc standby current with wdi max frequency i ccsw watchdog frequency = 1mhz,v cc = v cc(max) , 1hz, 32khz outputs disabled (note 5) 450 a battery test and trip (figures 17, 18, and 19) v batt trip point v btp internal mode 2.45 2.6 2.70 v trip input threshold v trip v cc = v cc(max) , v batt = 2v, external mode 1.14 1.24 1.31 v trip input comparatorhysteresis v trip_hyst 10 mv trip input current i trip_lkg external mode -100 +100 na battery test load r load_int internal 0.50 0.91 1.30 m test output-high voltage v test_high i test = -5ma v out - 0.3v v test output-low voltage v test_low i test = 5ma 0.3 v batt_lo , alm output v batt = 2v, v cc = 0, i ol = 5ma 0.5 v cc = 2.7v, v batt = 0, i ol = 10ma 0.5 output low voltage v ol v cc = 4.5v, v batt = 0, i ol = 20ma 0.5 v off-leakage i lkg -100 +100 na downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller _______________________________________________________________________________________ 5 dc electrical characteristics (continued)(v cc = v cc(min) to v cc(max) , t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (notes 1, 2) parameter symbol conditions min typ max units batt_on output v batt = 2v, v cc = 0, i ol = 5ma 0.5 v batt = 2.7v, v cc = 0, i ol = 10ma 0.5 output low voltage v ol v batt = 4.5v, v cc = 0, i ol = 20ma 0.5 v off-leakage i lkg -100 +100 na reset max6917eo30 2.5 2.63 2.7 max6917eo33 2.8 2.93 3.0 reset threshold voltage v rst MAX6917EO50 4.1 4.38 4.5 v v rst hysteresis v hyst 30 mv max6917eo30 27 75 max6917eo33 37 90 v cc falling-reset delay t rpd v cc falling from v rst(max) to v rst(min) , measured from the beginning of v cc falling to reset low MAX6917EO50 50 120 s m ai n reset acti ve- ti m eout p er i od t rp 140 200 280 ms reset output voltage v ol reset asserted, i ol = 1.6ma, v batt = 2v, v cc = 0 0.2 v off-leakage i lkg -100 +100 na i 2 c digital inputs scl, sda input high voltage v ih 0.7 x v cc v input low voltage v il 0.3 x v cc v input hysteresis v hys 0.05 x v cc v input leakage current v in = 0 to v cc -100 +100 na input capacitance (note 8) 10 pf sda output low voltage v ol i ol = 4ma, v cc = v cc(min) 0.4 v frequency outputs (32khz and 1hz) v cc = 0, v batt = 2v, i ol = 100a 0.2 v cc = 2.7v, v batt = 0, i ol = 1ma 0.4 32khz and 1hzout low voltage v ol v cc = 4.5v, v batt = 0, i ol = 2ma 0.5 v downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 6 _______________________________________________________________________________________ note 1: v rst is the reset threshold for v cc . see the selector guide section. note 2: all parameters are 100% tested at t a = +85 c. limits overtemperature are guaranteed by design and are not production tested. parameter symbol conditions min typ max units fast i 2 c-bus timing (figure 2 (note 9)) scl clock frequency f scl (note 10) 800 400,000 hz bus timeout t timeout 12 s bus free time between stopand start conditions t buf 1.3 s hold time after (repeated)start conditions t hd:sta after this period, the first clock is generated 0.6 s repeated start conditionsetup time t hd:sta 0.6 s stop condition setup time t su:sto 0.6 s data hold time t hd:dat (notes 11, 14) 0 0.9 s data setup time t su:dat 100 ns scl low period t low 1.3 s scl high period t high 0.6 s scl/sda rise time (receiving) t r (note 12) 20 + 0.1 c b 300 ns scl/sda fall time (receiving) t f (notes 12, 13) 20 + 0.1 c b 300 ns scl/sda fall time (transmitting) t f (notes 12, 13) 20 + 0.1 c b 250 ns pulse width of spike suppressed t sp 0 50 ns capacitive load for each busline c b 400 pf battery-test timing (figure 18) battery test to batt_lo active t bl (note 8) 1 s battery-test cycle normal t btcn (note 8) 24 hr battery-test pulse width t btpw (note 8) 1 s ac electrical characteristics(v cc = v cc(min) to v cc(max) , t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units v cc = 0, v batt = 2v, i oh = -100a v out - 0.1v v cc = 2.7v, v batt = 0, i oh = -1ma v out - 0.3v 32khz and 1hzout high voltage v oh v cc = 4.5v, v batt = 0, i oh = -2ma v out - 0.4v v dc electrical characteristics (continued)(v cc = v cc(min) to v cc(max) , t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (notes 1, 2) downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller _______________________________________________________________________________________ 7 v cc -to-out voltage vs. temperature max6917 toc01 temperature ( c) v cc -to-out voltage (mv) 60 35 10 15 15 20 25 30 35 4010 -40 85 v cc = 3v v batt = 0v i out = 35ma v cc = 3.3v v batt = 0v i out = 35ma batt-to-out voltage vs. temperature batt-to-out voltage (mv) 1 2 3 4 5 6 7 8 9 10 0 max6917 toc02 temperature ( c) 60 35 10 15 -40 85 v cc = 0v v batt = 3v i out = 800 a v cc = 0v v batt = 2v i out = 400 a timekeeping current vs. temperature i batt ( a) 1.0 1.2 1.4 1.60.4 0.6 0.8 max6917 toc03a temperature ( c) 60 35 10 15 -40 85 scl = sda = v cc = 0v 1hz, 32khz outputs disabledxtal fail disabled v batt = 3v timekeeping current vs. temperature i batt ( a) 1.0 1.2 1.4 1.60.4 0.6 0.8 max6917 toc03b temperature ( c) 60 35 10 15 -40 85 v batt = 3v scl = sda = v cc = 0v 1hz, 32khz outputs disabledxtal fail enabled typical operating characteristics (v cc = 3v, v batt = 3v, t a = +25 c, unless otherwise noted.) ac electrical characteristics (continued)(v cc = v cc(min) to v cc(max) , t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) note 3: i 2 c serial interface is operational for v cc > v rst . note 4: see the detailed description section (v out function). note 5: i batt is specified with sda = scl = v cc , ce_in = wdi = gnd, v out , ce_out , and mr floating. i ccs is specified with sda = scl = v cc , ce_in = wdi = gnd, v out , ce_out , and mr floati ng. note 6: i 2 c serial interface operating at 400khz, sda pulled high, and wdi = v cc or gnd, v out and ce_out floating. note 7: for out switchover to batt, v cc must fall below v rst and v batt . for out switchover to v cc , v cc must be above v rst or above v batt . note 8: guaranteed by design. not subject to production testing. note 9: all values are referred to v ih (min) and v il(max) levels. note 10: minimum scl clock frequency is limited by the max6917 bus timeout feature, which resets the serial bus interface if either sda or scl is held low for 1s to 2s. when using the burst read or write command, all 96 bytes of ram must be read/writtenwithin the timeout period. see the timeout feature section. note 11: a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ih(min) of the scl signal) to bridge the undefined region of the falling edge of scl. note 12: c b is the total capacitance of one bus line in pf. note 13: the maximum t f for the sda and scl bus lines is specified at 300ns. the maximum fall time for the sda output stage t f is specified at 250ns. this allows series-protection resistors to be connected between the sda/scl pins and the sda/scl buslines without exceeding the maximum specified t f . note 14: the maximum t hd:dat only has to be met if the device does not stretch the low period (t low ) of the scl signal. downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 8 _______________________________________________________________________________________ timekeeping current vs. temperature i batt ( a) 2.8 3.0 3.2 3.42.2 2.4 2.6 max6917 toc03c temperature ( c) 60 35 10 15 -40 85 v batt = 3v scl = sda = v cc = 0v 1hz, 32khz outputs enabledxtal fail disabled 185 190 195 200 210205 215 220180 reset timeout period (ms) reset timeout period vs. temperature max6917 toc04 temperature ( c) 60 35 10 15 -40 85 reset comparator delay vs. v cc falling max6917 toc05 v cc falling (v/ms) reset delay ( s) 100 10 1 10 100 1000 1 0.1 1000 reset comparator delay ( s) 10 15 20 25 30 35 40 45 50 5 reset comparator delay vs. temperature max6917 toc06 temperature ( c) 60 35 10 15 -40 85 v cc falling at 10v/ms 2.620 2.625 2.630 2.635 2.640 2.645 2.650 2.655 2.660 2.665 2.670 2.6752.615 reset threshold vs. temperature (max6917eo30) reset threshold (v) max6917 toc07 temperature ( c) 60 35 10 15 -40 85 reset goes high abovethis threshold reset goes low belowthis threshold 185 190 195 200 210205 215 220180 watchdog timeout period vs. temperature watchdog timeout period (ms) max6917 toc08 temperature ( c) 60 35 10 15 -40 85 wd time bit set to 1 maximum transient duration vs. reset comparator overdrive max6917 toc09 overdrive (mv) maximum transient duration ( s) 450 400 150 200 250 300 350 30 40 50 60 70 80 90 100 20 100 500 reset asserts above this line chip-enabled propagation delay vs. ce_out load capacitance max6917 toc10a load capacitance (pf) chip-enabled propagation delay (ns) 90 80 10 20 30 50 60 40 70 1 2 3 4 5 6 7 80 01 0 0 rising edge of ce_in to rising edge of ce_out v cc = 3.3v v cc = 3v v cc = 5v chip-enabled propagation delay vs. ce_out load capacitance max6917 toc10b load capacitance (pf) chip-enabled propagation delay (ns) 90 80 10 20 30 50 60 40 70 1 2 3 4 5 6 7 80 0 100 falling edge of ce_in to falling edge of ce_out v cc = 3.3v v cc = 3v v cc = 5v typical operating characteristics (continued) (v cc = 3v, v batt = 3v, t a = +25 c, unless otherwise noted.) downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller _______________________________________________________________________________________ 9 active supply current vs. supply voltage max6917 toc11a supply voltage (v) i cca (ma) 5.1 4.7 3.9 4.3 3.5 3.1 0.030 0.035 0.040 0.045 0.050 0.055 0.060 0.065 0.070 0.075 0.080 0.0850.025 2.7 5.5 scl = 400khz, sda = v cc 1hz, 32khz outputs enabledxtal fail enabled t a = -40 c, +25 c, +85 c active supply current vs. supply voltage max6917 toc11b supply voltage (v) i cca (ma) 5.1 4.7 3.9 4.3 3.5 3.1 0.030 0.035 0.040 0.045 0.050 0.055 0.060 0.065 0.070 0.075 0.0800.025 2.7 5.5 scl = 400khz, sda = v cc 1hz, 32khz outputs disabledxtal fail disabled t a = -40 c, +25 c, +85 c i batt ( a) 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.000.50 max6917 toc12a 5.0 4.5 3.5 4.0 3.0 2.5 2.0 5.5 t a = +85 c t a = +25 c t a = -40 c scl = sda = v cc = 0v 1hz, 32khz outputs disabledxtal fail disabled timekeeping current vs. supply voltage v batt (v) i batt ( a) 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.000.50 timekeeping current vs. supply voltage max6917 toc12b v batt (v) 5.0 4.5 3.5 4.0 3.0 2.5 2.0 5.5 t a = +85 c t a = +25 c t a = -40 c scl = sda = v cc = 0v 1hz, 32khz outputs disabledxtal fail enabled i batt ( a) 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.03.0 2.5 2.0 1.5 1.0 max6917 toc12c 5.0 4.5 3.5 4.0 3.0 2.5 2.0 5.5 t a = +85 c t a = +25 c t a = -40 c scl = sda = v cc = 0v 1hz, 32khz outputs enabledxtal fail disabled timekeeping current vs. supply voltage v batt (v) v cc to v out vs. output current (normal mode) max6917 toc13 output current (ma) v cc to v out drop (v) 90 80 70 60 50 40 30 20 10 0.01 0.02 0.03 0.04 0.05 0.06 0.080.07 0 0 100 v cc = +2.7v v cc = +3.3v v cc = +5v v batt -to-v out vs. output current (battery backup mode) max6917 toc14 output current (ma) v batt -to-v out drop (v) 2.0 1.6 1.2 0.8 0.4 0.005 0.010 0.015 0.020 0.025 0 0 2.4 v batt = +3.3v v batt = +2v v batt = +5v typical operating characteristics (continued) (v cc = 3v, v batt = 3v, t a = +25 c, unless otherwise noted.) downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 10 ______________________________________________________________________________________ pin description pin name function 1v out supply output for external sram or other ics requiring use of backup-battery power. when v cc rises above the reset threshold or above v batt , v out is connected to v cc . when v cc falls below v reset and v batt , v batt is connected to v out . connect a 0.1f low-leakage bypass capacitor from v out to gnd. leave open if not used. 2 test external battery test. active high for 1s during each battery test. intended to drive an external mosfetor bipolar transistor for an external battery-test configuration. external test must be selected in the control register to use test; otherwise, it remains low. leave open if not used. 3 trip external trip set. if a different battery-low threshold is desired other than the internal por default ofv btp , then connect r set+ between v batt and trip and r set- between trip and the drain or collector of an external transistor whose base or gate is connected to test; figure 17 (see the battery test section). external test must be selected in the control register to use trip. leave open if not used. 4 batt_on open-drain battery-on indicator. batt_on is active low when the max6917 is powered from v batt . 5 ce_in chip-enable input. the input to the chip-enable gating circuitry. connect ce_in to gnd if unused. 6 mr manual-reset input. a logic low on mr asserts reset . reset remains asserted as long as mr is low and for t rp after mr returns high. the active-low mr input has an internal pullup resistor. mr can be driven from a ttl or cmos-logic line or shorted to ground with a switch. internal debouncing circuitryensures noise immunity. leave mr open if unused. 7 wdi watchdog input. if wdi remains either high or low for longer than the watchdog timeout period, theinternal watchdog timer runs out and reset is asserted. the internal watchdog timer clears while reset is asserted or when wdi sees a rising or falling edge. the watchdog function can be disabled from thecontrol register. the timeout period is configurable in the control register for 200ms or 1.6s. 8 gnd ground 9 x1 32.768khz crystal-oscillator input 10 x2 32.768khz crystal-oscillator output downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 11 detailed description functional description the max6917 contains eight 8-bit timekeeping registers,seven 8-bit alarm threshold registers, one status register, one control register, one alarm-configuration register, and 96 x 8 bits of sram. in addition to single-byte reads and writes to registers and ram, there is a burst timekeeping register read/write command, a burst ram read/write command, and a battery-test command that allows soft- ware-commanded testing of the backup battery at any time. an i 2 c-bus-compatible interface allows serial com- munication with a p. when v cc is less than the reset threshold, the serial interface is disabled to prevent erro- neous data from being written to the max6917. a p supervisory section and an nvram controller are provid- ed for ease of implementation with p-based systems. a crystal fail-detect circuit and a data-valid bit can be used to guarantee ram data integrity and valid timekeeping data. two reference frequencies outputs, 32.768khz and 1hz, are provided for external device clocking. time and calendar data are stored in a binary-coded decimal (bcd) format. figure 1 shows the functional diagram of the max6917. real-time clock the rtc provides seconds, minutes, hours, day, date,month, and year information. the end of the months is automatically adjusted for months with fewer than 31 days, including corrections for leap years through 2099. crystal oscillator the max6917 uses an external, standard 6pf loadwatch crystal. no other external components are required for this timekeeping oscillator. power-up oscil- lator start time is dependent mainly upon applied v cc and ambient temperature. the max6917, because ofits low timekeeping current, exhibits a typical startup time of 1s to 2s. i 2 c-compatible interface the i 2 c bus allows bidirectional, 2-wire communication between different ics. the two lines are serial data line(sda) and serial clock line (scl). both lines must be connected to a positive supply through individual pullup resistors (see the typical application circuit) . data transfer can only be initiated when the bus is not busy (both sda and scl are high). figure 2 shows a timing diagram for i 2 c communication. pin description (continued) pin name function 11 32khz 32.768khz output. buffered push-pull output that is enabled from the fout configuration register. 12 1hz 1hz output. buffered push-pull output that is enabled from the fout configuration register. 13 sda open-drain data input/output. i 2 c bus serial data input/output connection. 14 scl serial clock input. i 2 c bus clock for input/output data transfers. 15 alm open-drain, active-low alarm output. alm goes low when rtc time matches alarm thresholds set in the alarm threshold registers. alm stays low until cleared by reading or writing to the alarm configuration register or to any of the alarm threshold registers. 16 ce_out chip-enable output. ce_out goes low only when ce_in is low and reset is not asserted. if ce_in is low when reset is asserted, ce_out remains low for t rce or until ce_in goes high, whichever occurs first. ce_out is pulled to v out . 17 batt_lo open-drain, battery-low indicator. batt_lo is active low when the v batt input is tested below v btp if the internal trip is selected in the control register (por default). if external trip is selected in the controlregister, then batt_lo is active low when trip is less than v trip . 18 reset open-drain, active-low reset output. reset pulses low for t rp when triggered, and stays low whenever v cc is below the reset threshold or when mr is logic low. reset remains low for t rp after either v cc rises above the reset threshold or mr goes from low to high. 19 v cc main supply input. connect a 0.1f bypass capacitor from v cc to gnd. 20 v batt backup-battery input. when v cc falls below the reset threshold and v batt , v out switches from v cc to v batt . when v cc rises above v batt or the reset threshold, v out reconnects to v cc . v batt may exceed v cc . connect v batt to gnd if no backup-battery supply is used. connect a 0.1f low-leakage bypass capacitor from v batt to gnd. downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 12 ______________________________________________________________________________________ watchdog timer debounce circuit reset logic reset ce control ce_out oscillator 32.768khz crystal- fail detect dividers seconds minutes hours date month day year control century alarm config batt test status config alarm thresholds fout config ram burst power control and monitor control logic input- shift registers address register 96 x 8 ram data valid logic alarm control logic xtal fail clock burst max6917 wdi mr x1x2 ce_in test 32khz 1hz trip gnd v batt v out v cc batt_lo batt_on scl sda alm figure 1. functional diagram downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 13 to maximize battery life and prevent erroneous datafrom being entered into the max6917, the serial bus interface is disabled when v cc is below v rst . if the sda or scl serial interface lines are held low for longerthan 1s to 2s, the serial bus interface resets and awaits for a new start condition (see the start and stop conditions section). i 2 c system configuration a device on the i 2 c-compatible bus that generates a message is called a transmitter and a device thatreceives the message is called a receiver. the device that controls the message is the master and the devices that are controlled by the master are called slaves (figure 3). the word message refers to data in the form of three 8-bit bytes for a single read or write. the first byte is the slave id byte, the second byte is the address/command byte, and the third is the data. start and stop conditions data transfer can only be initiated when the bus is notbusy (both sda and scl are high). a high-to-low tran- sition of sda while scl is high defines a start (s) condition; low-to-high transition of sda while scl is high defines a stop (p) condition (figures 2, 4). any time a start condition occurs, the slave id must follow immediately, regardless of completion of a previous data transfer. bit transfer after the start condition occurs, 1 bit of data is trans-ferred for each clock pulse. the data on sda must remain stable during the high portion of the clock pulse as changes in data during this time are interpreted as a control signal (figure 5). acknowledge the acknowledge bit is a clocked 9th bit that the recipi- ent uses to handshake receipt of each byte of data (figure 6). thus, each byte transferred effectively requires 9 bits. the master generates the 9th clock pulse, and the recipient pulls down sda during the acknowledge clock pulse, such that the sda line is sta- ble low during the high portion of the clock pulse. a master receiver must signal an end of data to the trans- mitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case, the transmitter must leave the sda high to enable the master to generate a stop condition. if a stop condition is received before the current byte of data transfer is completed in burst mode, the last incomplete byte is ignored if it is a burst transaction to ram or the whole burst transaction is ignored if it is a burst trans- action to the timekeeping registers. there is no limit to the number of bytes that can be transmitted between a start and a stop condition. slave address before any data is transmitted on the i 2 c-bus-compati- ble serial interface, the device that is expected torespond must be addressed first. the first byte sent after the start (s) condition is the address byte or 7- bit slave id. the max6917 acts as a slave trans- mitter/receiver. therefore, scl is only an input clock signal and sda is a bidirectional data line. the slave address for the max6917 is shown in figure 7. sda scl t f t r t low t su:dat t f t hd:sta t hd:dat t high t su:sta t hd:sta t sp t su:sto t r t buff p s s sr s = start condition p = stop condition sr = repeated start condition figure 2. i 2 c communication timing diagram downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 14 ______________________________________________________________________________________ address/command byte the second byte of data sent after the start condition is the address/command byte (figure 8). each data transfer is initiated by an address/command byte. bits 7C 1 specify the designated register or ram location to be read or written to, and the lsb (bit 0) specifies awrite operation if logic zero or a read operation if logic one. the command byte is always input starting with the msb (bit 7). reading from the timekeeping registers the timekeeping registers (seconds, minutes, hours,date, month, day, and year) and the control register can be read either with a single read or a burst read (figure 9). since the rtc runs continuously and a read takes a finite amount of time, there is the possibility that the clock counters could change during a read opera- tion, thereby reporting inaccurate timekeeping data. in the max6917, each clock counter s data is buffered by a latch. clock counter data is latched by the i 2 c bus read command (on the falling edge of scl when the slave acknowledge bit is sent, after the address/com- mand byte has been sent by the master to read a time- keeping register). collision-detection circuitry ensures that this does not happen coincident with a seconds counter update to ensure accurate time data is being read. this avoids time-data changes during a read operation. the clock counters continue to count and keep accurate time during the read operation. if single reads are used to read each of the timekeep-ing registers individually, then it is necessary to do some error checking on the receiving end. an error can occur when the seconds counter increments before all the other registers are read out. for example, suppose a carry of 13:59:59 to 14:00:00 occurs during single- read operations of the timekeeping registers. then the net data could become 14:59:59, which is erroneous real-time data. to prevent this with single-read opera- tions, read the seconds register first (initial seconds) and store this value for future comparison. when the remaining timekeeping registers have been read out, read the seconds register again (final seconds). if the initial seconds value is 59, check that the final-seconds value is still 59; if not, repeat the entire single-read process for the timekeeping registers. a comparison of the initial-seconds value with the final-seconds value can indicate if there was a bus-delay problem in read- ing the timekeeping data (difference should always be 1s or less). using a 100khz bus speed, and sequential single reads, it would take under 2.5ms to read all seven of the timekeeping registers plus a second read of the seconds register. the most accurate way to read the timekeeping regis- ters is to perform a burst read. with burst reads, the main timekeeping registers (seconds, minutes, hours, date, month, day, year) and the control register are read sequentially, in the order listed with the seconds register first. they must be all read out as a group of sda scl master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver figure 3. i 2 c system configuration sda scl start condition stop condition sp figure 4. start and stop conditions sda scl data line stable; data valid change of data allowed figure 5. bit transfer scl sda by transmitter clock pulse for acknowledge start condition sda by receiver 12 89 s figure 6. acknowledge downloaded from: http:///
eight registers, with 8 bytes each, for proper executionof the burst-read function. all seven timekeeping regis- ters are latched upon the receipt of the burst-read com- mand. the worst-case error that can occur between the actual time and the read time is 1s. writing to the timekeeping registers the time and date can be set by writing to the time- keeping registers (seconds, minutes, hours, date, month, day, year, and century). to avoid changing the max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 15 sda scl 11 10 0 0 0r / w msb lsb ack figure 7. max6917 slave address a7 a6 a5 a4 a3 a2 a1 r/ w bit 7 bit 0 figure 8. address/command byte figure 9. read and write operations r/ w r/ w r/ w r/ w r/ w 1 acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave 1010000 0 addr 8-bit data p 11010000 1 addr 8-bit data no acknowledge from master no acknowledge from master p sr 11010001 11010000 0 addr last 8-bit data s p 11010000 1 addr ss r first 8-bit data first 8-bit data acknowledge from master 11010001 r/ w last 8-bit data p single writesingle read burst write burst read start condition start condition start condition start condition repeated start condition stop condition stop condition stop condition repeated start condition addr = 7-bit ram or register address s = start condition sr = repeated start condition p = stop condition a s = acknowledge from slave a m = acknowledge from master a m = not acknowledge from master a s a s a s a s a s a s a s a s a s a s a s a s a m a m a m a s s s downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 16 ______________________________________________________________________________________ current time by an incomplete write operation, the cur-rent time value is buffered from being written directly to the clock counters. the new data sent replaces the cur- rent contents of this input buffer. this time update data is loaded into the clock counters after the stop bit at the end of the i 2 c bus write operation. collision-detection circuitry ensures that this does not happen coincidentwith a seconds-counter update to guarantee that accu- rate time data is being written. this avoids time data changes during a write operation. an incomplete write operation aborts the time-update procedures and the contents of the input buffer are discarded. the clock counters reflect the new time data beginning with the first 1s clock cycle after the stop bit. the clock counter is reset immediately after a write to the seconds regis- ter or a burst write to the timekeeping registers. this ensures that 1s clock tick is synchronous to timekeep- ing writes. if single-write operations (figure 9) are used to write to each of the timekeeping registers, then error checking is needed. if the seconds register is the one to be updat- ed, update it first and then read it back and store its value as the initial seconds. update the remaining time- keeping registers and then read the seconds register again (final seconds). if initial seconds was 59, ensure it is still 59. if initial seconds was not 59, ensure that final seconds is within 1s of initial seconds. if the seconds register is not to be written to, then read the seconds register first and save it as initial seconds. write to the required timekeeping registers and then read the sec- onds register again (final seconds). if initial seconds was 59, ensure it is still 59. if initial seconds was not 59, ensure that final seconds is within 1s of initial seconds. although both single writes and burst writes are possi- ble, the most accurate way to write to the timekeeping counters is to do a burst write (figure 9). in the burst write, the main timekeeping registers (seconds, min- utes, hours, date, month, day, year) and the control register are written sequentially. they must be all writ- ten to as a group of eight registers, with 8 bytes each, for proper execution of the burst-write function. all seven timekeeping registers and the control register are simultaneously loaded into the input buffer at the end of the 2-wire bus write operation. the worst-case error that can occur between the actual time and the write time update is 1s. to avoid rollover issues when writing time data to themax6917, the remaining time and date registers must be written within 1s of updating the seconds register when using single writes. for burst writes, all eight reg- isters must be written within this period (1s). the weekday data in the day register increments at midnight. values that correspond to the day of the week are user defined, but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on). if invalid values are written to the timekeeping registers, the operation becomes undefined. timeout feature the purpose of the bus timeout feature is to reset the seri- al bus interface and change the sda line of the max6917 from an output to an input, which puts the sda line into a high-impedance state. this is necessary when the max6917 is transmitting data and becomes stuck at a logic-low level. if the sda line is stuck low, any other device on the bus is not able to communicate. the timeout feature looks for a valid start and stop condition to determine whether sda has been stuck low. a valid start condition initiates the timeout counter in reference to the internal 1hz clock. counting begins on the first rising edge of the 1hz clock after a valid start condition. if a valid stop condition is detected before the next rising edge of the 1hz clock, the timeout counter is stopped and awaits a new valid start condition. if a valid stop condition is not detected before the next rising edge of the 1hz clock, the i 2 c interface resets to the idle state and waits for a new i 2 c transaction. depending on the occurrence of the start condition, that initiates the timeout counter,in reference to the internal 1hz clock, the timeout peri- od can be 1s to 2s. the lower limit of the timeout period (1s) imposes a limit on the scl frequency of the max6917 because a burst read/write requires up to 96 bytes of information to be transmitted in between a start and stop condition. downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 17 registers tables 1 and 2 show the register map, as well as theregister descriptions for the max6917. control register the control register contains bits for configuring themax6917 for custom applications. bit d0 (batt on blink) and d1 (batt lo blink) are used to enable a 1hz blink rate on batt_on and batt_lo when they are active; see the battery test section for details. d2 (wd time) and d3 (wd en) are used to enable thewatchdog function and select its timeout. for details, see the watchdog input section. d5 (int/ext test) sets whether the internal resistor ratio or an externalresistor ratio is to be used to check for the low-battery condition; see the battery test section for details. d6 (xtal en) enables the crystal-fail-detect circuitry whenset. see the crystal-fail detect section for details. d7 (wp) is the write protect bit. before any write operationto the registers (except the control register) or ram, bit 7 must be zero. when set to one, the write-protect bit prevents write operations to any register (except the control register) or ram location. timekeeping and alarm thresholds registers time and date data is stored in the timekeeping andalarm threshold registers in bcd format as shown in table 1. the weekday data in the day register is user defined (a common format is 1 = sunday, 2 = monday, etc.) am/pm and 12hr/24hr mode for both timekeeping and alarm threshold registers(table 1), d7 of the hours register is defined as the 12hr or 24hr mode-select bit. when set to one, the 12hr mode is selected. in the 12hr mode, d5 is the am /pm bit with logic one being pm. in the 24hr mode, d5 is thesecond 10hr bit (20hr to 23hr). clock-burst mode addressing the clock-burst register specifies burst-mode operation. in this mode, the first eight clock/cal- endar registers (seven timekeeping and the control register) can be consecutively read or written to by using the address/command byte 00h for a write or 01h for a read (table 1). if the write-protect bit is set to one when a write-clock/calendar-burst mode is specified, no data transfer occurs to any of the seven timekeeping registers or the control register. when writing to the clock/calendar registers in the burst mode, the first eight registers must be written to for the data to be transferred. ram the static ram consists of 96 x 8 bits addressed con-secutively in the ram address/command space. even address/commands (3eh to fch) are used for ram writes and odd address/commands (3fh to fdh) are used for ram reads (table 2). ram-burst mode sending the ram-burst address/command (feh forwrite, ffh for read) specifies burst-mode operation. in this mode, the 96 ram locations can be consecutively read or written to starting with bit 7 of address/com- mand 3eh for writes, and 3fh for reads. a burst read outputs all 96 bytes of ram. when writing to ram in burst mode, it is not necessary to write all 96 bytes for the data to transfer; each complete byte written is transferred to the ram. when reading from ram, data are output until all 96 bytes have been read, or until the data transfer is stopped by the i 2 c master. status register the status register contains individual bits for monitor-ing the status of several functions of the max6917. bits d0 C d3 are unused and always read zero (table 1). d4 (alm out) reflects the state of the alarm function; seethe alarm-generation function section for details. d5 (batt lo) indicates the state of the battery connectedto v batt ; see the battery test section for more informa- tion. d6 (data valid) alerts the user if all power waslost. see the data valid bit section for details. d7 (xtal fail) is the output of the crystal-fail detect circuit. seethe crystal-fail detect section for details. downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 18 ______________________________________________________________________________________ table 1. register map clock burst 0 0 0 0 0 0 0 a0 a1 a2 a3 a4 a5 a6 a7 function d0 d1 d2 d3 d4 d5 d6 d7 0000000 value 000000 0 10 sec 1 sec 0?9 por state sec 0000000 00000 1 0 0 10 min 1 min 0?9 por state min 0 0 00 0 00000 1 0 12/ 24 10 hr 1 hr 00?3 por state hr am / pm 10 hr 000 01?2 0000000 0000 1 0 1 0 10 date 1 date 01?8/2901?0/31 por state date 0000000 0000 1 0 1 0 10 m 1 month 01?2 por state month 00 0000000 0000 1 1 1 0 weekday 01?7 por state day 0000 0111000 0000 1 1 0 1 year 00?9 por state year 10 year 0 01 0 000 1 00 1 wp por state control int/ ext test 000 xtal en 0 wd en wd time batt lo blink batt on blink 0001100 000 1 00 1 100 year 00?9 por state century 1000 year 0 00 0 000 1 0 1 0 one sec por state alarm configuration day 000 year month date hr min sec 0 11 0 000 1 1 0 0 32khz v cc en 32khz v batt en 1khz v cc en 1khz v bat en por state status 000 0000 0 00 0 0 xtal fail por state batt lo 000 data valid alm out 0000 0 register address register function 0 por state defines the power-on reset state of the register. r w 1 r w r w r w r w r w r w r w r w 0 1 0 1 0 1 0 r w r w r w 1 00 1 1 0 1 0 0 fout configuration r w 0 downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 19 table 1. register map (continued) batt test 0001101 a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 0111111 value 0 1 1 1 0 0 1 10 sec 1 sec 0?9 por state sec 0111111 1 1 1 1 0 0 1 0 10 min 1 min 0?9 por state min 0 1 10 1 0 0 0 0 1 0 1 12/ 24 10 hr 1 hr 00?3 por state hr am / pm 10 hr 111 01?2 0011111 1 0 0 0 1 0 1 0 10 date 1 date 01?8/2901?0/31 por state date 0001111 0 1 0 0 1 0 1 0 10 m 1 month 01?2 por state month 00 0000011 1 1 0 0 1 0 1 0 week day 01?7 por state day 0000 1111111 0 0 1 0 1 0 1 1 year 00?9 por state year 10 year 1 0 1 0 1 0 test configuration (factory reserved) xxxxxxx 1 1 1 1 1 0 x ram data 0 00h-ffh ram 0 0 1 1 1 1 1 1 1 1 1 1 1 0 register address register function 0 0000000 0 por state alarmthresholds: ram registers: xxxxxxx x ram data 95 00h-ffh ram 95 . . . . . . ram burst 0 por state defines the power-on reset state of the register. w r w r w r w r w r w r w r w r w r w r w r 00 0 0 0 0 0 0 0 1 1 function downloaded from: http:///
power control v batt provides power as a battery backup. v cc pro- vides the primary power in dual-supply systems wherev batt is connected as a backup source to maintain timekeeping in the absence of primary power. whenv cc rises above the reset threshold, v rst , v cc powers the max6917. when v cc falls below the reset thresh- old, v rst , and is less than v trd , v batt powers the max6917. if v cc falls below the reset threshold, v rst , and is more than v tru , v cc still powers the max6917. v cc slew rate in power-down is limited to 10v/ms (max) for proper data retention. v out function v out is an output supply voltage for battery-backed-up devices such as sram. when v cc rises above the reset threshold or is greater than v batt ,v out connects to v cc (figure 19). when v cc falls below v rst and v batt , v out connects to v batt . there is a typical 100mv hysteresis associated with the switchingbetween v cc and v batt on the v out output. connect a 0.1f capacitor from v out to gnd. power-on reset (por) the max6917 contains an integral por circuit thatensures all registers are reset to a known state on power- up. once either v cc or v batt rises above 1.6v (typ), the por circuit releases the registers for normal operation.when v cc or v batt drops to less than 0.9v (typ), the max6917 resets all register contents to the por defaults. oscillator start time the max6917 oscillator typically takes 1s to 2s to beginoscillating. to ensure the oscillator is operating correct- ly, the system software should validate proper time- keeping. this is accomplished by reading the seconds register. any reading with more than 0s, from the por value of 0s, is a validation of proper startup. alarm-generation function the alarm function is configured using the alarm-con- figuration register and the alarm-threshold registers (table 1). writing a one to d7 (one sec) in the alarm- configuration register sets the alarm function to occur once every second, regardless of any other setting in the alarm-configuration register or in any of the alarm- threshold registers. when the alarm is triggered, d4 (alm out) in the status register is set to one and the open-drain alarm output alm goes low. the alarm is cleared by reading or writing to the alarm-configurationregister or by reading or writing to any of the alarm- threshold registers. this resets the alm output to a high and the alm out bit to zero. when d7 (one sec) is set to zero in the alarm-configu- ration register, then the alarm function is set by the remaining bits in the alarm-configuration register and the contents of the respective alarm-threshold register. for example, writing 01h (0000 0001) to the alarm-con- figuration register causes the alarm to trigger every time the seconds-timekeeping register matches the seconds alarm-threshold register (i.e., once every minute on a specific second). writing 02h (0000 0010) to the alarm configuration register causes the alarm to trigger on a minutes match (i.e., once every hour). writing a 4fh (0100 1111) to the alarm configuration register causes the alarm to be triggered on a specific second, of a specific minute, of a specific hour, of a specific date, of a specific year. when setting the alarm-threshold registers, ensure that both the hour-timekeeping register and the hour-alarm- threshold register are using the same-hour format (either 12hr or 24hr format). the alarm function, as well as the alm output, is opera- tional in both v cc and battery-backup mode. max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 20 ______________________________________________________________________________________ downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 21 table 2. hex register address and description write address/command (hex) read address/command (hex) description por setting (hex) 00 01 clock burst n/a 02 03 seconds 00 04 05 minutes 00 06 07 hour 00 08 09 date 01 0a 0b month 01 0c 0d day 01 0e 0f year 70 10 11 control 48 12 13 century 00 14 15 alarm configuration 19 16 17 fout configuration c0 18 19 status 00 1a n/a battery test n/a 1c 1d seconds alarm threshold 7f 1e 1f minutes alarm threshold 7f 20 21 hours alarm threshold bf 22 23 date alarm threshold 3f 24 25 month alarm threshold 1f 26 27 day alarm threshold 07 28 29 year alarm threshold ff 2a 2b test configuration 00 3e 3f ram 0 indeterminate 40 41 ram 1 indeterminate 42 43 ram 2 indeterminate 44 45 ram 3 indeterminate 46 47 ram 4 indeterminate ???? ???? ???? f4 f5 ram 91 indeterminate f6 f7 ram 92 indeterminate f8 f9 ram 93 indeterminate fa fb ram 94 indeterminate fc fd ram 95 indeterminate fe ff ram burst indeterminate downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 22 ______________________________________________________________________________________ crystal-fail detect the crystal-fail detect circuit looks for a loss of oscillationfrom the 32.768khz oscillator for 30 cycles (typ) or more. both the control register and the status register are used in the crystal-failure detection scheme (table 1). the crystal-fail detect circuit sets the xtal fail bit in the status register to one for a crystal failure and to zero for normal operation. once the status register is read, the xtal fail bit is reset to zero, if it was previously one. if the crystal-fail-detect circuit continues to sense a failed crystal, then the xtal fail bit is set again. on initial power-up, the crystal-fail detect circuit is enabled. since it takes a while for the low-power, 32.768khz oscillator to start, the xtal fail bit in the status register can be set to one indicating a crystal failure. the xtal fail bit should be polled a number of times to see if it is set to zero for successive polls. if the polling is far enough apart, a few polled results could guarantee that a maximum of 10s had elapsed since power-on, at which time the oscillator would be consid- ered truly failed if the xtal fail bit remains one. on subsequent power-ups, when xtal en is set to one, if xtal fail is set to one, time data should be considered suspect. the crystal-fail-detection circuit functions in both v cc and v batt modes when the xtal en bit is set in the control register. manual reset input a logic low on mr asserts reset . reset remains asserted while mr is low, and for t rp after it returns high (figure 10). mr has an internal pullup resistor, so it can be left open if it is not used. internal debouncecircuitry requires a minimum low time on the mr input of 1s with 35ns maximum glitch immunity. reset output a p s reset input starts the p in a known state. the max6917 s p supervisory circuit asserts a reset to prevent code-execution errors during power-up, power-down, and brownout conditions. the reset output is guaranteed to be active for 0v < v cc < v rst , provided v batt is greater than v batt (min). if v cc drops below and then exceeds the reset threshold, an internal timerkeeps reset active for the reset timeout period t rp ; after this interval, reset becomes inactive high. this condition occurs at either power-up or after a v cc brownout. the reset output is also activated when the watchdog interrupt function is enabled but no transition is detect-ed on the wdi input. in this case, reset is active for the period t rp before becoming inactive again. when reset is active, all inputs wdi, mr , ce_in , sda, and scl are disabled. the max6917eo30 is optimized to monitor 3.0v 10%power supplies. except when mr is asserted, reset is not active until v cc falls below 2.7v (3.0v - 10%), but is guaranteed to occur before the power supply fallsbelow 2.5v (3.0v - 15%). the max6917eo33 is optimized to monitor 3.3v 10% power supplies. except when mr is asserted, reset is not active until v cc falls below 3.0v (3.0v is just above 3.3v - 10%), but is guaranteed to occur before thepower supply falls below 2.8v (3.3v - 15%). the MAX6917EO50 is optimized to monitor 5.0v 10% power supplies. except when mr is asserted, reset is not active until v cc falls below 4.5v (5.0v - 10%), but is guaranteed to occur before the power supply fallsbelow 4.1v (4.1v is just below 5.0v - 15%). negative-going v cc transients the max6917 is relatively immune to short-duration nega- tive transients (glitches) while issuing resets to the p dur- ing power-up, power-down, and brownout conditions. therefore, resetting the p when v cc experiences only small glitches is usually not recommended. typically, av cc transient that goes 150mv below the reset threshold and lasts for 90s or less does not cause a reset pulse to be issued. a 0.1f capacitor mounted close to the v cc pin provides additional transient immunity. mr ce out ce in reset t rce t rp t rp figure 10. manual-reset timing diagram downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 23 interfacing to ps with bidirectional reset pins microprocessors with bidirectional reset pins, such asthe motorola 68hc11 series, can contend with the max6917 reset output. if, for example, the reset output is driven high and the p wants to pull it low,indeterminate logic levels can result. to correct this, connect a 4.7k resistor between the reset output and the p reset i/o as shown in figure 11. buffer the reset output to other system components. battery-on output the battery-on output, batt_on , is an open-drain out- put that indicates when the max6917 is powered fromthe backup-battery input, v batt . when v cc falls below the reset threshold, v rst , and below v batt , v out switches from v cc to v batt and batt_on becomes low. when v cc rises above the reset threshold, v rst , v out reconnects to v cc and batt_on becomes high (open-drain output with pullup resistor). if desired, thebatt_on output can be register selected, through the batt on blink bit in the control register, to toggle onand off 0.5s on, 0.5s off when active. the por default is logic zero for no blink. watchdog input the watchdog circuit monitors the p s activity. if the p does not toggle the watchdog input (wdi) within theregister-selectable watchdog-timeout period, reset is asserted for t rp . at the same time, the wd en and wd time bits in the control register (table 1) are reset to zero and can only be set again by writing the appropri- ate command to the control register. thus, once a reset is asserted due to a watchdog timeout, the watchdog function is disabled (figure 12). wdi can detect pulses as short as t wdi . data bit d2 in the control register controls the selection of the watch-dog-timeout period. the power-up default is 1.6s (d2 = 0). a reset condition returns the timeout to 1.6s (d2 = 0). if d2 is set to one, then the watchdog-timeout period is changed to 200ms. data bit d3 in the control register is the watchdog-enable function. a logic zero disables the watchdog function, while a logic one enables it. the por state of wd en is logic one, or the watchdog func- tion is enabled. disable the watchdog function by writ- ing a zero to the wd en bit in the control register, within the 1.6s por default timeout after power-up. wdi does not include a pulldown or pullup feature. for this reason, wdi should not be left floating. when the wd en bit in the control register is set to zero, wdi should be connected to v cc or gnd. wdi is disabled and does not draw cross-conduction current when v cc falls below v rst . watchdog software considerations there is a way to help the watchdog-timer monitor soft- ware execution more closely, which involves setting and resetting the watchdog input at different points in the program rather than pulsing the watchdog input. this technique avoids a stuck loop, in which the watchdog timer would continue to be reset within the loop, keeping the watchdog from timing out. figure 13 shows an example of a flow diagram where the i/o driving the watchdog input is set high at the beginning of the pro- gram, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. if the program should hang in any sub- routine, the problem would quickly be corrected sincethe i/o is continually set low and the watchdog timer is allowed to time out, causing a reset to be issued. max6917 v cc gnd v cc gnd reset reset buffer 4.7k p v cc figure 11. interfacing to p with bidirectional reset i/o v rst v cc reset wdi t rp t rp t wd t wd wd en and wd time are setto zero and the watchdog function is disabled. figure 12. watchdog timing diagram downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 24 ______________________________________________________________________________________ chip-enable gating internal gating of chip-enable (ce) signals preventserroneous data from corrupting external sram in the event of an undervoltage condition. the max6917 uses a transmission gate from ce_in to ce_out (figure 14). during normal operation ( reset inactive), the transmis- sion gate is enabled and passes all ce transitions.when reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the external sram. the short ce propagation delay from ce_in to ce_out enables the max6917 to be used with most ps. if ce_in is low when reset asserts, ce_out remains low for t rce to permit completion of the current write cycle. chip-enable input the ce transmission gate is disabled and ce_in is high impedance (disabled mode) while reset is active. during a power-down sequence when v cc passes the reset threshold, the ce transmission gate disables and ce_in immediately becomes high impedance if the voltage atce_in is high. if ce_in is low when reset becomes active, the ce transmission gate disables at the momentce_in goes high or t rce after reset is active, whichever occurs first (see the chip-enable timing diagram). this permits the current write cycle to complete during power-down. the ce transmission gate remains disabled and ce_in remains high impedance (regardless of ce_in activity) for most of the reset-timeout period (t rst ) any time a reset is generated. when the ce transmission gate is enabled, the impedance of ce_in appears as a 46 (typ) load in series with the load at ce_out . the propagation delay through the ce transmissiongate depends on v cc , the source impedance of the driver connected to ce_in , and the loading on ce_out (see the chip-enable propagation delay vs. ce_out load capacitance graph in the typical operating characteristics ). for minimum propagation delay, the capacitive load at ce_out should be mini- mized, and a low-output-impedance driver should beused on ce_in (figure 15). start set wdi high program code subroutine of program loop set wdi high return figure 13. watchdog flow diagram max6917 chip-enable output control reset generator v out ce_out ce_in figure 14. chip-enable gating max6917 25 equivalent source impedance 50 cable 50 3.6v vcc c l 10pf gnd v cc 50 ce_in ce_out batt c l includes load capacitance and scope probe capacitance. figure 15. propagation delay test circuit downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 25 chip-enable output when the ce transmission gate is enabled, the imped-ance seen at ce_out is equivalent to a 46 (typ) resistor in series with the source driving ce_in . in the disabled mode, the transmission gate is off and anactive pullup connects ce_out to v out (see figures 14, 16). this pullup turns off when the transmissiongate is enabled. test configuration register this is a read-only register. data valid bit data valid has a por setting of zero, indicating thatthe data in the max6917 rtc is not guaranteed to be valid (table 1). a read of the status register sets the data valid bit to one, indicating valid data in the max6917 rtc. in a system that uses a backup power supply, the data valid bit should be set to one by the system software on first system power-up by reading the status register. after that, any time the system recovers from a reset condition caused by v cc < v rst , the data valid bit can be read to see if the data stored duringoperation from the backup power supply is still valid (i.e., the backup power supply did not drop out). a one indi- cates valid data and a zero indicates corrupted data. any time the internal supply to the max6917 (either v batt or v cc depending upon the operating conditions) drops below 1.5v to 1.6v (typ), the data valid bit is setto zero even if it has recently been set by a read of the status register. v cc reset ce_out ce_in 2.0v v rst t rp t rp v batt v cc t ced t rce t rpd v rst figure 16. chip-enable timing diagram downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 26 ______________________________________________________________________________________ battery test battery-test normal operation in normal operation, the battery-test circuitry uses thecontrol register por settings of int/ext test, which is set to logic low as default (table 1). in this mode, all bat- tery-test load resistors and threshold settings are internal. when v cc rises above v rst , the max6917 automatically performs one power-on battery monitor test. additionally,a battery check is performed every time that a reset is issued, either from a manual reset or a watchdog timeout. after that, periodic battery voltage monitoring at the facto- ry-programmed time interval of 24hr begins while v cc is applied.after each 24hr period (t btcn ) has elapsed, the max6917 connects v batt to an internal 0.91m (typ) test resistor (r set+_int + r set-_int ) for 1s (t btpw ) (figure 17). during this 1s, if v batt falls below the fac- tory-programmed battery trip point v btp , the open- drain, battery-low output, batt_lo , is asserted active low and the batt lo bit in the status register is set toone. the batt lo output can be register selected to toggle at a 1hz rate (0.5s on, 0.5s off) when active.once batt lo is active, the 24hr tests stop until a fresh battery is inserted and batt lo is cleared by writing any data to the battery test register at address 0x0d (figure 18). writing to this register performs a battery test and provided that the fresh battery is not low, deactivates the batt lo output and resets batt lo in the status register. normal 24hr testing resumes.if a different load or batt lo thresholds are desired for testing the backup battery, then external program resis-tors can be used in conjunction with the trip and test inputs (see the battery test-control register and other test options section). battery replacement following batt_lo activation should be done with v cc nominal and not in battery- backup mode so that sram data is not lost.alternatively, if sram data need not be saved, the bat- tery can be replaced with the v cc supply removed. if a battery is replaced in battery-backup mode, sufficienttime must be allowed for the voltage on the v out out- put to decay to zero. this ensures that the freshness-seal mode of operation has been reset and is active when v cc is powered up again. if insufficient time is allowed, then v cc must exceed v batt during the sub- sequent power-up to ensure that the max6917 has left battery-backup mode (figure 19). the max6917 does not constantly monitor an attached battery because such monitoring would drastically reduce the life of the battery. as a result, the max6917 max6917 1.24v v cc batt_lo control logic r set+_int 480k r set-_int 430k v out int/ext test = 0 ( 5ma) batt test test trip vbatt batt_lo r set+_ext r load_ext (optional) r set-_ext q ext int/exttest figure 17. max6917 battery load and test circuit downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 27 only tests the battery for 1s every 24hr. if a good bat-tery (one that has not been previously flagged with batt_lo ) is removed between battery tests, the max6917 does not immediately sense the removal anddoes not activate batt_lo until the next-scheduled battery test. for this reason, a software-commandedbattery test should be performed after a battery replacement by writing any data to the battery-test reg- ister at address 1ah. battery monitoring is only a useful technique when test- ing can be done regularly over the entire life of a lithium battery. because the max6917 only performs battery monitoring when v cc is nominal, systems that are pow- ered down for excessively long periods can completelydrain their lithium cells without receiving any advanced warning. to prevent such an occurrence, systems using the max6917 battery-monitoring feature should be powered up periodically (at least every few months) to perform battery testing. furthermore, anytime batt_lo is activated on the first battery test after a power-up, data integrity should be checked through achecksum or other technique. timekeeping data would also be suspect and should be checked for accuracy against an accurate known reference. t btcn t btpw t bl once the battery is detected as low, the periodic battery testing ceases. a battery check can be initiated by writing to the register 0x1a. v rst v cc v batt battery- test active batt_lo v btp (battery test point) figure 18. battery-test timing diagram v cc v batt 0v v out 0v v rst v batt v rst v rst v rst exit freshnessseal mode freshnessseal reset v batt connected to v out v cc connected to v out v batt connected to v out v cc connected to v out v batt connected to v out v batt floating v batt floating battery attach battery detach battery attach battery detach figure 19. battery switchover diagram downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 28 ______________________________________________________________________________________ freshness-seal mode when the battery is first attached to the max6917 withoutv cc power applied, the device does not immediately pro- vide battery-backup power to v out (figure 19). only after v cc exceeds v rst and later falls below both v rst and v batt does the max6917 leave freshness-seal mode and provide battery-backup power. this mode allows abattery to be attached during manufacturing but not used until after the system has been activated for the first time. as a result, no battery energy is drained during storage and shipping. battery-test control register and other test options there are two warning formats for the batt_lo and batt_on outputs. by setting d0 (batt on blink) and/or d1 (batt lo blink) in the control register to one,the respective warning output toggles on every 0.5s and off every 0.5s when set to active low by the internal max6917 logic. this allows a more noticeable warning indicator in systems where an led is connected as a sta- tus or warning light for the end user. the por default set- tings of zero leave these outputs set to logic low when they are active. d5 (int/ext test) selects whether the battery-test cir- cuit is configured as internal or external (table 1). if d5 is set to zero (default value), then the internal resistor- divider is used between v batt and gnd to select the battery-low trip point (figure 17). the internal resistors, r set+_int and r set-_iint , are used to divide v batt in half, as well as to provide the battery-test-load resis- tance of 0.91m (typ). if d5 (int/ext test) is set to one, then the two externalresistors, r set+_ext and r set-_ext , are used to divide v batt down to the ratio for a trip point set at trip of 1.24v (v trip ) (typ). r set+_ext plus r set-_ext in series provide the load resistance used during the 1s every-24hr-battery test. if additional load resistance is desired, then an external load resistor, r load_ext , can be placed between v batt and the collector or drain of the transistor driven by test. the equivalent load resis-tance used to test the battery is then r load_ext in par- allel with the series combination of r set+_ext plus r set-_ext . in this mode, the internal resistors are removed from trip and are not used as a load duringthe battery-test pulse. test pulses high to perform the battery test and remains low between tests. one final battery-test feature of the max6917 is the software write address/command of 1ah that forces a 1s battery test to be performed every time it is sent. frequency outputs the 1hz and 32khz (32.768khz) frequency outputsprovide buffered, push-pull outputs for timing or clock- ing of external devices. each push-pull output is refer- enced to gnd for logic-low output levels and referenced to v out for logic-high output levels. disabled frequency outputs are held at a logic-low level. the fout configuration register (table 1) con- tains individual enable bits that control the state of the respective frequency output for v cc operating mode and for v batt operating mode. bits d5 (32khz vbatt en) and d4 (1hz vbatt en) inthe fout configuration register enable the respective frequency output when operating from v batt , if set to one, or disable the respective frequency output if set tozero. por settings disable all frequency outputs when operating from v batt . rf rd cd12pf cg 12pf external crystal x1 x2 max6917 figure 20. oscillator functional schematic * * * * * * * * * **** ** x2 * guard ring ground plane via connection ground plane via connection sm watch crystal *layer 1 trace * **layer 2 local ground plane connect only to pin 8 ground plane via connection max6917 x1 groundplane via connection figure 21. crystal layout downloaded from: http:///
bits d7 (32khz vcc en) and d6 (1hz vcc en) in thefout configuration register enable the respective fre- quency output when operating from v cc , if set to one, or disable the respective frequency output if set tozero. por settings enable both output frequencies when operating from v cc . applications information crystal selection connect a 32.768khz watch crystal directly to the max6917 through pins 9 and 10 (x1, x2) (figure 20). use a crystal with a specified load capacitance (c l ) of 6pf. refer to applications note 616: considerations for maxim real-time clock crystal selection from the maxim website (www.maxim-ic.com) for more informa-tion regarding crystal parameters and crystal selection, as well as a list of crystal manufacturers. when designing the pc board, keep the crystal as close to the x1 and x2 pins of the max6917 as possi- ble. keep the trace lengths short and small to reduce capacitive loading and prevent unwanted noise pickup. place a guard ring around the crystal and tie the ring toground to help isolate the crystal from unwanted noise pickup. keep all signals out from beneath the crystal and the x1 and x2 pins to prevent noise coupling. finally, an additional local ground plane on an adjacent pc board layer can be added under the crystal to shield it from unwanted pickup from traces on other lay- ers of the board. this plane should be isolated from the regular pc board ground, tied to the gnd pin of the max6917, and needs to be no larger than the perime- ter of the guard ring. ensure that this ground plane does not contribute to significant capacitance between the signal line and ground on the connections that run from x1 and x2 to the crystal. see figure 21. for frequency stability overtemperature, refer to the applications note: real-time-clock selection and opti- mization from the maxim website (www.maxim-ic.com.) max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 29 chip information process: cmos downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 30 ______________________________________________________________________________________ user reset n 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v led n.c. crystal 3.3v 0.1 f 0.1 f 3.0v 0.1 f n.c. n.c. n.c. batt_lo batt_on x1 x2 v cc v batt mr alm sda scl 1hz ce_in reset wdi test trip 32khz v out ce_out max6917 gnd gnd ce i/o p1.0 rst cs int1 scl sda into c gnd cmos sram typical application circuit 2019 18 17 16 15 14 13 12 3 4 5 6 7 8 v batt v cc resetbatt_lo batt_on trip test v out top view ce_outalm scl sda gnd wdi mr ce_in 1211 9 10 1hz32khz x2 x1 max6917 qsop pin configuration part supply voltage (v) max6917eo30 3.0 max6917eo33 3.3 MAX6917EO50 5.0 selector guide downloaded from: http:///
max6917 i 2 c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 31 ? 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qsop.eps e 1 1 21-0055 package outline, qsop .150", .025" lead pitch downloaded from: http:///

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